Multi-card inference topology: request-boundary aggregation on a latency-bound LAN
Ran Tao (Octoryn Research)
Abstract
Design note downstream of a cross-box latency result: a sub-millisecond consumer-Ethernet LAN makes within-layer tensor-parallel decode a regression, so aggregation must happen at the request boundary. The ranking (estimates, not measurements) puts data-parallel first (0 hops/token, prototype-stage; aggregate throughput is an HONEST heterogeneous sum across differing models, not a single-model scale-up) and pipeline second (~2 hops/token, a modest multiplier from low-latency transport tuning). A resident-memory rule keeps a 128GB Apple Silicon box single-resident, grounded in a real OOM crash.
1. Thesis / Contribution
Claimed. Given a latency-bound LAN (the premise: cross-box tensor-parallel decode regresses on a sub-millisecond consumer-Ethernet link per a companion technical report, because the LAN's bandwidth is ample but its latency is decisive), the correct shape for multi-box Apple Silicon inference is to aggregate at the request boundary, never within the layer. The design ranking that follows is: data-parallel (0 hops/token) first, pipeline parallel (~2 hops/token) second, within-layer tensor-parallel rejected for decode on this interconnect.
NOT claimed. This is a design/architecture note, not a measured-throughput report. The headline aggregate figure (a several-tens-of-tokens-per-second range across a small multi-box HTTP daemon) is a design estimate and an honest heterogeneous sum — it is NOT the single-model decode rate of one ~30B model, NOT a verified production measurement, and NOT a linear single-model scale-up. The pipeline multiplier (roughly 1.5-2.5x) is a design estimate, not a measured production figure. No generation-quality, parity, or benchmark-scale claim is made here. The data-parallel path is stated as prototype-stage (near-complete, not finished), i.e. not a completed-and-benchmarked system.
2. Design
The interconnect is bandwidth-ample but latency-bound, so all aggregation is placed at the request boundary.
| Rank | Approach | Hops/token | Status | Design estimate | Mechanism / requirement |
|---|---|---|---|---|---|
| 1 | Data-parallel | 0 | Prototype (small multi-box HTTP daemon) | Aggregate throughput, heterogeneous sum | Each box serves whole requests independently |
| 2 | Pipeline parallel | ~2 | Not built (design) | ~1.5-2.5x throughput | Self-managed low-latency transport that disables small-packet coalescing (Nagle-style stalls) |
| — | Within-layer tensor-parallel | per-layer barriers | Rejected for decode | Regression | Structurally wrong for decode on this LAN (per companion latency report) |
Iron rule (resident-memory constraint). On a 128GB Apple Silicon box, the data-parallel path must stay single-resident: never co-load two ~30B-class models. The resident set of two such models alone would exceed RAM and trigger swap / the memory watchdog. This is grounded in a real out-of-memory incident (a lesson learned), not a hypothetical.
3. Evidence / Status
| Claim | Basis | Maturity |
|---|---|---|
| Tensor-parallel decode regresses on the consumer-Ethernet LAN | Companion technical report (cross-box latency result) | Measured elsewhere; cited premise, not re-measured here |
| Data-parallel is 0-hop and near-complete | Small multi-box HTTP daemon prototype | Prototype, not benchmarked in this note |
| Aggregate data-parallel throughput range | Design estimate, heterogeneous sum | Estimate, NOT a measured figure |
| Pipeline ~1.5-2.5x throughput | Design estimate | Estimate, not built |
| Two ~30B-class co-load exceeds 128GB -> swap/watchdog | Real out-of-memory incident (cited lesson) | Observed incident |
There is no Results table in the conventional sense because this note presents no first-party measurements of its own — every quantitative figure is either an estimate or a value imported from a separately-reported incident/report. Presenting an empirical-style results table here would overclaim.
4. Limitations (harsh)
- The headline throughput is an estimate, not a measurement. It carries no run count, no variance, no single-model decomposition. It is explicitly a sum across heterogeneous models of differing quality, so it cannot be read as the decode rate of a single ~30B model.
- The pipeline multiplier is unbuilt. No code, no measurement; it is a paper estimate that depends on a not-yet-implemented self-managed low-latency transport.
- The premise is borrowed. The decisive "tensor-parallel regresses" finding is measured in a companion report, not reproduced here; this note inherits whatever sample-size and single-interconnect limits that report carries.
- Single interconnect. All reasoning is specific to a sub-millisecond consumer-Ethernet LAN between Apple Silicon boxes. On a low-latency interconnect (NVLink-class), within-layer tensor-parallel may be viable and this ranking could invert.
- The experimental evidence level is generous for this note. This note itself contributes a design argument plus one observed incident; its quantitative core is estimates. The label is retained per provenance rules but should be read as "experimental premise, design conclusion," not "experimentally validated throughput."
- Prototype-stage is not finished. The remaining integration, failover, and routing behaviour under concurrent load are unverified here.
5. Provenance / Relation
- Type: Architecture paper. Status: Published.
- Relation: Directly downstream of the companion cross-box tensor-parallel latency technical report (the "tensor-parallel regresses on consumer-Ethernet" premise).
- Hardware: Apple Silicon Mac boxes over a consumer-Ethernet LAN (128GB-class boxes; small multi-box cluster). Build/run commands for the data-parallel daemon: not recorded in source notes.
- Reproducibility caveat: the central premise should be re-validated against the companion latency report before this design ranking is relied upon; the throughput estimates are unvalidated by construction.
Claim boundary
The author's explicit scope — what this work does and does not establish — carried over from the Octoryn Research publishing model.
Proves
- Given a latency-bound LAN, request-boundary aggregation is the correct design: data-parallel (0 hops/token, prototype-stage, aggregate throughput as a heterogeneous-model sum ESTIMATE) first, pipeline parallel (about two hops/token, a modest multiplier estimate) second.
- A 128GB-class Apple Silicon box must stay single-resident (never co-load two ~30B-class models), grounded in a real out-of-memory incident.
Does not prove
- That the aggregate throughput is a single-model scale-up (it is a heterogeneous sum) or a measured figure (it is a design estimate).
- Pipeline figures beyond the design-estimate multiplier (not yet built or measured).
- Behaviour on low-latency interconnects (where tensor-parallel may be viable).
- Generation quality, parity, or benchmark-scale throughput of any kind.
Applies when
- Aggregating inference across Apple Silicon boxes over a latency-bound (sub-millisecond consumer-Ethernet) LAN.
Does not apply when
- Low-latency interconnects, single-box multi-GPU, single-model linear-scaling claims, or any context demanding measured (not estimated) throughput.
Authors
- Ran Tao — Investigation, Writing
Cite this
Citation
Tao, R., Octoryn Research. (2026). Multi-card inference topology: request-boundary aggregation on a latency-bound LAN (AP-2026-0003). Octopus Research Institute.
BibTeX
@techreport{oriap20260003,
title = {Multi-card inference topology: request-boundary aggregation on a latency-bound LAN},
author = {Tao, Ran and {Octoryn Research}},
institution = {Octopus Research Institute},
year = {2026},
note = {Permanent ID AP-2026-0003. Not peer reviewed.}
}Disclosures
- Funding
- Hardware and infrastructure provided by Octoryn / Octopus Core Pty Ltd.
- Conflicts of interest
- Octoryn ships commercial inference and governance tooling; findings are reported independently.
